Memory cell defects and memory array defects have many sources and, as a result, many signatures. While single, isolated cell failures may be scattered throughout the array, very often, multiple cells in the same vicinity fail. When multi-cell failures occur, these failures may be characterized as a word line failure, (i.e. failing cells with the same word line address), a bit (or column) line failure (i.e. failing cells with the same bit address), or both. The sources of these multi-cell failures vary. Consequently, memory arrays are tested extensively to identify defective cells.
FIG. 1 is a schematic representation of a prior art wide Input/Output (I/O) 16 Mb DRAM chip. The chip 100 is organized with two Redundant Bit Lines (RBL) 102 and 104 providing two spare columns in each subarray 106. Each subarray 106 includes 2.sup.n Bit Line (BL) pairs 108 (where n is typically between 5 and 8) and one or more redundant bit line pairs (2 in this example). As used hereinafter, reference to a bit line refers to a complementary pair of lines. Each of the subarrays 106 is part of a subarray block 110. All of the subarray blocks 110, collectively, form the entire RAM array. So, for example, a 16Mb RAM has 16 blocks 110 of 1Mb each. Block size, subarray size and the number of subarrays 106 per block 110 are interdependent and, selected based on performance and design objectives.
Multiple bits of a subarray block 110 are accessed (read from or written to) when one word line 112 is selected and driven high. Data from accessed cells are provided simultaneously to the bit lines 108 and redundant bit lines 102 and 104. After a predetermined minimum delay, a delay sufficient to allow the redundancy decoder to determine whether a spare column is addressed, a single bit line 108 or a redundant bit line 102, 104 is selected in each subarray 106. In each subarray, the selected bit line 108 or redundant bit line 102, 104 is coupled to a Local Data Line (LDL) 114. LDLs 114 are coupled to Master Data Lines (MDLs) 116. The MDLs 116 couple corresponding subarrays 106 in each subarray block 110. Data is transferred between the subarrays 106 and the chip I/O's on the MDLs 116.
FIG. 2 is a transistor level cross-sectional schematic of a bit line 108 in a subarray 106. Cells 120, 122 connected to adjacent word lines 112, 118 also are connected to opposite lines 124, 126 of each bit line pair. Thus, half of the word lines 112 (e.g., word lines with even addresses) select cells 120 on one line 124 of the bit line pair. While the remaining half of the word lines 118, (odd addressed word lines) select the cells 122 on the other lines 126 of the bit line pair. Each cell's storage capacitor (C.sub.S) 128 is, typically, a trench capacitor or a stacked structure for array density. Each bit line 124, 126 has essentially the same capacitance (C.sub.BL).
As is known in the art, the maximum voltage that an FET will pass is its gate voltage (V.sub.G) reduced by the FET's turn-on or threshold voltage (V.sub.T), i.e., the storage capacitors 128, 138 voltage V.sub.S =V.sub.GS -V.sub.T. The magnitude of the bit line signal is C.sub.S * V.sub.S /(C.sub.S +C.sub.BL) During a write, if a bit line 124, 126 (C.sub.BL) is charged to the supply voltage level V.sub.dd (also referred to as V.sub.h) and if the word line 112, 118 is also at V.sub.dd, then V.sub.S =V.sub.dd -V.sub.T. Normally, the bit lines are pre-charged to some known voltage, e.g. V.sub.dd /2, prior to reading a cell. Therefore, the bit line signal V.sub.SIG =C.sub.S (V.sub.S -V.sub.dd /2)/(C.sub.S +C.sub.BL). With V.sub.S =V.sub.dd -V.sub.T or 0, then either V.sub.SIG =C.sub.S (V.sub.dd /2-V.sub.T)/(C.sub.S +C.sub.BL) or, V.sub.SIG =-C.sub.S (V.sub.dd /2)/(C.sub.S +C.sub.BL). So, to maximize bit line signal V.sub.SIG, the word line 112, 118 is boosted during a write, typically, to at least V.sub.dd +V.sub.T so that V.sub.S =V.sub.dd is written into the cell. This boosted level, called V.sub.pp, is normally generated on-chip. With V.sub.pp=V.sub.dd +V.sub.T, V.sub.SIG =.+-.C.sub.S (V.sub.dd /2)/(C.sub.S +C.sub.BL).
The circuit of FIG. 2A operates according to the timing diagram of FIG. 2B. A "one" is stored in any cell 120, 122 by charging the cell's storage capacitor 128, 138. Prior to selecting a cell 120 or 122, the array is at its steady-state standby or pre-charge condition. The voltage on the bit line pair 124, 126 is pulled to V.sub.dd /2 and equalized by equalization transistor 134 because equalization signal EQ on its gate 132 is high. The Word Lines (WL) 112,118 and Column SeLect (CSL) lines 136 are held low during standby. In prior art RAMs, each word line was clamped low (unless driven high) by a simple resetable latch (not shown).
When the chip's Row Address Strobe signal (RAS) is asserted indicating the array is to be accessed. EQ is pulled low, isolating the bit line pair from each other and from the V.sub.dd /2 pre-charge supply, floating the individual lines of the pair at V.sub.dd /2. A selected word line 112 (or 118) is driven high. The cell's access gate 130 is turned on in each cell 120 on the selected word line 112, coupling the accessed cell's storage capacitor 128 to line 124 of the bit line pair. Thus, V.sub.SIG develops when charge is transferred between the storage capacitor 128 and line 124. The other line 126 of the bit line pair 124,126 remains at its pre-charge voltage level V.sub.dd /2 and serves as a reference voltage for the sense amplifier 140.
Typically, bit line capacitance is at least one order of magnitude larger than the storage capacitor 128. So, V.sub.SIG is normally at least an order of magnitude smaller than V.sub.dd. To maximize charge transfer between the bit line 124 and the storage capacitor 128, the word line 112 is boosted to V.sub.pp .gtoreq.V.sub.dd +V.sub.t. Thus, one line of the pair (124 or 126) remains at V.sub.dd /2, while the other ( 126 or 124 ) is driven to V.sub.dd /2+V.sub.SIG =(V.sub.dd /2) (1+C.sub.S) / (C.sub.S +C.sub.BL).
After a delay sufficient to develop V.sub.SIG, i.e. to transfer V.sub.S to the bit line, the sense amp 140 is set by driving the Sense Amp Enable (SAE) line 142 high and, subsequently, by pulling its inverse (SAE) 144 low. V.sub.SIG is amplified and re-driven on the bit line pair 124, 126 by the sense amp, which forces 124,126 High/Low or Low/High depending on data stored in the cell 120. Simultaneously with re-driving the bit line pair, the sense amp writes the sensed data back into the selected cell 120. Once all of the bit lines 124, 126 have been re-driven, a Column SeLect signal (CSL) rises to activate the column decoder for column i. So, driving CSL 146 high selects column i in each accessed subarray 106 by connecting the selected column i bit line pair 124,126 to the LDLs 148, 150 through pass gates 152, 154.
One source of cell failures stems from inadequate (cell) signal margin. During initial manufacturing tests, at ideal operating conditions, all of the cells may appear good. However, in writing some cells, not all of the charge may be stored nor retained (known as a weak "1") or C.sub.S may not be fully discharged (known as a weak "0"). In other than ideal operating conditions, these cells may not consistently reflect the data written into them. Such a failing cell may appear acceptable under test conditions, but when used in system memory, the cell may fail, intermittently. So, it is important to identify such cells (with marginal stored data levels) during test.
FIG. 3 represents a bit line pair 124, 126 upon which cell signal margin may be tested by a prior art approach. In this prior art test, the bit line pre-charge voltage V.sub.PRE is varied. Normally, as described for FIG. 2A, .PHI..sub.EQ 132 iS high during restore and low during sense. Pre-charge FETs 156,158 are connected between V.sub.PRE and bit lines 126,124 respectively. Under normal operating conditions, V.sub.PRE is set to V.sub.dd /2. However, during test, V.sub.PRE is intentionally varied to reduce V.sub.SIG and change the sense amp reference voltage. Since V.sub.PRE is varied form V.sub.dd /2, V.sub.SIG =C.sub.S (V.sub.S -V.sub.PRE)/(C.sub.S +C.sub.BL) so, for example, if V.sub.PRE is reduced below V.sub.dd /2, the difference between V.sub.PRE and 0V is reduced so that the 0 data signal is reduced.
However, raising or lowering V.sub.PRE affects the sense amp 140 operation in ways unrelated to signal margin. If, for example V.sub.PRE &lt;V.sub.TN, then, when SAE is driven high to set the sense amps, neither of the sense amp cross coupled NFETs may turn on. Sensing is therefore through the significantly slower cross coupled PFETs. So, on prior art RAMs, to insure that the sense amps function correctly, V.sub.PRE cannot be reduced below V.sub.TN. Furthermore, because V.sub.SIG is dependant upon V.sub.PRE, varying V.sub.PRE significantly from V.sub.dd /2 alters the time it takes for V.sub.SIG to develop. Altering this time makes it difficult to determine whether testing failures are due to poor signal margin and, therefore, real or, instead, the result of not allowing adequate time for signal development and, therefore, false errors.
Other prior art signal margin test schemes required additional chip space for reference cells or for special test circuitry. These other prior art signal margin test schemes also were not very reliable.